Patent attributes
An apparatus and method for single instruction multiple data caching includes a memory access request generator operative to receive a primary access request. The method and apparatus further includes a cache controller coupled to the memory access request generator, wherein the cache controller is operative to execute a memory request. The method and apparatus further includes a memory interface coupled to the cache controller, the memory interface operative to retrieve a plurality of requested data. The method and apparatus further includes a request processor coupled to the cache controller, the memory interface and the memory access request generator. The request processor is operative to receive a plurality of requested data and thereupon generate a plurality of parallel data outputs therefrom.
