Patent attributes
The invention relates to an integrated electronic device for digital signal processing, which includes a phase locked loop for generating an output clock signal based on a reference clock input signal, multiple outputs for providing multiple representatives of the output clock signal, a stage for generating a phase shifted output clock signal having multiple phases spanning one clock period of the output clock signal, a register having multiple units each coupled by a data input to a representative of the output clock signal, and to the phase shifted output clock signal for storing single bit values in response to an edge of the shifted output clock signal, wherein the stage for generating the phase shifted output clock is controlled to selectively shift the phase of the output clock and circuitry for reading out the stored single bit values from the register is provided in order to determine the output skew of the output clock signals based on the read out single bit value.