US Patent 7596731 Test time reduction algorithm

Exemplary embodiments provide a method and system for reducing test time for electronic devices. The method and system aspects include receiving a test data file containing results from a set of tests run on a first set of devices; determining a frequency of failure metric for each of the tests from the test data file; classifying each one of the tests as redundant or necessary based on the frequency of failure metric determined for each of the tests; and creating a reduced set of tests that includes the necessary test but does not include the redundant tests.