Patent attributes
A nonvolatile ferroelectric memory device is provided which includes a cell array including a plurality of nonvolatile memory cells each configured to read/write data, a refresh control unit configured to control a refresh operation in a given cycle in response to a refresh control signal for improving retention characteristics of data stored in the plurality of nonvolatile memory cells to output a count address for refresh operations, a row address control unit configured to latch and decode a row address inputted in response to a RAS signal and an output signal from the refresh control unit and to select the count address, a column address control unit configured to latch and decode a column address inputted in response to a CAS signal, and an input/output logic circuit configured to control read/write operations of the cell array in response to an output enable signal and read/write commands.
