Patent 7600208 was granted and assigned to Cadence Design Systems on October, 2009 by the United States Patent and Trademark Office.
Disclosed are methods, systems and apparatus for automatically placing decoupling capacitors in an integrated circuit to compensate for voltage drops that might otherwise occur in a power grid. In one embodiment of the invention, the method includes generating one or more regions of the integrated circuit design, with each region having one or more cells, determining an amount of decoupling capacitance required in each region of the integrated circuit design by analyzing each cell in the region, and adding sufficient decoupling capacitor cells to the region to compensate for the potential voltage drop.