US Patent 7600211 Toggle equivalence preserving logic synthesis

A method of synthesis of a second circuit (N2) that is toggle equivalent to a first circuit (N1), comprising building up N2 in topological order, starting from the input side of N2, by producing a sequence of subcircuit designs N2(1) through N2(k), such that output toggling of circuit N1 implies output toggling of subcircuit N2(1) for every i=1, . . , k; and output toggling of N2(j) strictly implies output toggling of N2(i) if i<j.