Patent attributes
A method of processing semiconductor wafers comprises forming a pattern of recesses in an exposed surface of each wafer in a lot, prior to an epitaxy step. At least one recessed test structure is included in the pattern of recesses. At least one dimension of the recessed test structure is determined prior to the epitaxy step, then a corresponding dimension of an epitaxial structure grown above the recessed test structure in the epitaxy step is measured. A deviation between the dimension of the recessed test structure and the dimension of the epitaxial structure is determined and, from the deviation, the process temperature at which the epitaxy step was performed is determined. In case the deviation exceeds a predetermined limit, the temperature in the process chamber is adjusted for a subsequent lot of wafers to be processed.
