US Patent 7602015 Process to control semiconductor wafer yield

The size of BVDSS distribution is controlled by the active manipulation of the distribution of silicon parameters across a wafer to offset opposing effects inherent in the wafer fabrication process. Thus, the resistivity of the silicon wafer is increased toward the edge of the wafer. This offsets the drop-off of BVDSS across the wafer caused in wafer fabrication by deeper trenches at the edge of the wafer. This causes a flatter BVDSS profile across the wafer and significantly reduced BV distribution over the wafer.