US Patent 7602049 Capacitive techniques to reduce noise in high speed interconnections

Improved methods and structures are provided using capacitive techniques to reduce noise in high speed interconnections, such as in CMOS integrated circuits. Embodiments of an electronic device having a transmission line circuit include a first layer of electrically conductive material on a substrate and a first layer of insulating material on the first layer of the electrically conductive material. The first layer of insulating material has a thickness of less than 1.0 micrometers (μm). A transmission line is formed on the first layer of insulating material and a second layer of insulating material is formed on the transmission line. A second layer of electrically conductive material is formed on the second layer of insulating material.