Patent attributes
A circuit for providing a bit string, the circuit including a plurality of commonly wired, substantially identical bit cells in a string, where each bit cell is designed to read as only one of a logical high and a logical low upon a given input, and each bit cell comprises a bit in the bit string. An enable line is associated with each of the bit cells, where each enable line has a fuse that is adapted to be activated upon application of a signal by a tester. Each bit cell is configured so as to be logically isolated from all others of the plurality of bit cells in the string when the fuse associated with the bit cell is activated. The circuit is adapted such that bit cells having fuses that are activated are logically removed from the bit string.
