US Patent 7605625 Device, system and method of delay calibration

System and method of calibrating delay mismatch for high-spectral purity applications. For example, a method includes measuring the delay of one delay element at a time in a fixed topology by moving a time reference generated by an auxiliary delay-locked loop. The auxiliary DLL may have a replica structure of the primary DLL being calibrated. The calibration method uses one output clock signal of the primary DLL and measures delay mismatch using a reference phase previously measured using the same topology. The calibration method takes into account all delay mismatches in the topology up to the primary DLL output clock signal, including any delay generated by an associated multiplexer.