US Patent 7606057 Metal line layout in a memory cell

A memory cell includes polysilicon gates 2 running in a first direction. A sequence of layers metal lines includes a layer of bit lines 4 running in a second direction substantially orthogonal to the first direction followed by data lines 6 running in that second direction and then word lines 8 running in the first direction. The data lines 6 are precharged to a value which is held whilst the bit lines 4 are being used to sense data values stored within a memory cell.