US Patent 7606086 Nonvolatile semiconductor memory device

A nonvolatile semiconductor memory device comprises a memory cell array in which memory cells are arranged in a row and column direction, a circuit for applying a first voltage to a selected bit line, a circuit for applying a second voltage to unselected bit lines and word lines, a circuit for reading a current flowing in a selected memory cell, a voltage suppressor circuit for suppressing fluctuation of the second voltage with respect to each word line and bit line provided in the circuit for applying the second voltage, and a second voltage control circuit for applying the first voltage to the selected bit line and a dummy second voltage to the unselected bit lines and the word lines during the preset period and controlling the voltage suppressor circuit during a reading period so that the second voltage may fluctuate in a fluctuation direction of the first voltage.