Patent attributes
In the field of video displaying the low video levels do not generate large area flicker. For displaying video sources with higher frame rate, it is therefore the idea of the invention, to extract from two corresponding pixels of two successive video frames a common portion (Vx) that will be displayed at a sub-frequency fv/2 while the individual portions (V1′, V2′) of the corresponding pixels video are displayed at the correct high frequency fv. The time period for displaying two frames is divided into three sub-groups. Two groups of sub-fields with similar sizes, for displaying the individual portions (V1′, V2′) and one group of sub-fields, called extra-codes, for displaying the common portion (Vx). This enables to eliminate large area flicker artifacts from PDPs, when displaying 50 Hz based video norms by using upconverted 100 Hz video sequences and to display real high frequency video on the PDP (ca. up to 120 Hz) without frame dropping.
