Patent attributes
A memory circuit having dual-gate memory cells and a method for fabricating such a memory circuit are disclosed. The dual-gate memory cells each include a memory device and an access device sharing a semiconductor layer, with their respective channel regions provided on different surfaces of the semiconductor layer. The semiconductor layer has a thickness, such that when a pass voltage is applied to the gate electrode of the access device, the access device and the memory device remains isolated, such that the charge stored in the memory device is unaffected by the pass voltage. The pass voltage is determined from a range of voltages, when applied to the access device, has no effect on the threshold voltage of the memory device. The dual-gate memory cells can be used as building blocks for a non-volatile memory array, such as a memory array formed by NAND-strings. In such an array, during programming of a nearby memory device in a NAND string, in NAND-strings not to be programmed, if inversion regions are allowed to be formed in the semiconductor layer, or if the semiconductor layer is allowed to electrically float, electrical interaction exists between the access devices and the memory devices to inhibit programming of the memory devices.
