US Patent 7613956 Microcomputer capable of monitoring internal memory

A microcomputer comprises: a CPU which sequentially executes a program; an internal memory connected to the above CPU via an internal bus; a debug support unit, which monitors the internal state in response to an externally provided command; a monitor memory, which stores data stored in the internal memory, for being accessed by the debug support unit; and a monitor memory control unit, connected to the internal bus, which at a concurrent copy mode performs a control to concurrently write, to the monitor memory, data which is written to the internal memory in response to access from the internal bus, and at a monitor mode performs a control to read data in the monitor memory in response to access from the debug support unit.