US Patent 7616491 Semiconductor memory device improved in data writing

A bit line is shared by first and second NAND units. First and second selection transistors are connected in series between the bit line and the first NAND unit. Third and fourth selection transistors are connected in series between the bit line and the second NAND unit. A control unit changes a first and second signals and a potential of the bit line from a first level to a second level higher than a first level, and changes the potential of the bit line from the second level to the first level after changing the first signal from the second level to the first level.