Patent attributes
An integrated circuit load board includes a substrate on which a plurality of integrated circuit sockets and an integrated test circuit are mounted. The integrated test circuit includes circuitry for testing the timing margins of memory devices by determining the relative timing between read data and data strobe signals applied to a memory device. The relative timing between the read data and data strobe signals is determined by using a delay line to delay the data strobe signal over a range of delays, and determining a final delay that causes the transitions of the delayed data strobe signal to coincide with the transitions of the read data signals. The time corresponding to the final delay is then determined by using a phase interpolator to generate a range of phase offset signals having known delay times until a phase offset signal has the same delay as the final delay.
