US Patent 7620057 Cache line replacement with zero latency

A method for cache management includes assigning a respective cache line in a cache of a processing device to each of a plurality of processing flows in the processing device, and loading respective context data relating to each of the processing flows from a memory into the respective cache line that is assigned thereto. Respective activity levels of the processing flows are monitored. Responsively to detecting an absence of activity of a processing flow, and prior to receiving a request to overwrite the cache line, the context data are written back to the memory from the respective cache line that is assigned to the processing flow.