US Patent 7620135 Data processing apparatus that identifies a communication clock frequency

A data processing apparatus receives a message containing a sync break interval with a unique bit pattern and a sync field interval identified by the sync break interval. A timing property of the sync field interval specifies the length of bit periods of the message. A clock source circuit supplies a sampling clock signal to define time points for sampling bits from the message. The clock source circuit adapts a frequency of the sampling clock signal to the timing property of the sync field interval. The clock source circuit searches for potential sync break intervals that match the unique bit pattern for a range of bit period values and verifies for each potential sync break interval whether the sync field interval identified by that potential sync break interval specifies a bit period with a duration so that the sync break interval matches the unique pattern for the specified bit period, as a condition prior to supplying the sampling clock signal at the adapted frequency specified by the sync field interval identified by the potential sync break interval. Supply of sampling clock signals is preferably suppressed after an end of a preceding message until said condition is met.