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US Patent 7620791 Mapping memory in a parallel processing environment
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Patent
Date Filed
April 14, 2006
Date of Patent
November 17, 2009
Patent Application Number
11404207
Patent Citations Received
US Patent 12132648 System and method for facilitating efficient load balancing in a network interface controller (NIC)
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US Patent 11985060 Dragonfly routing with incomplete group connectivity
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US Patent 11991072 System and method for facilitating efficient event notification management for a network interface controller (NIC)
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US Patent 12003411 Systems and methods for on the fly routing in the presence of errors
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US Patent 12021738 Deadlock-free multicast routing on a dragonfly network
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US Patent 11750504 Method and system for providing network egress fairness between applications
US Patent 11757764 Optimized adaptive routing to reduce number of hops
US Patent 11757763 System and method for facilitating efficient host memory access from a network interface controller (NIC)
US Patent 11765074 System and method for facilitating hybrid message matching in a network interface controller (NIC)
US Patent 11777843 System and method for facilitating data-driven intelligent network
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Patent Inventor Names
David Wentzlaff
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Matthew Mattina
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Anant Agarwal
0
Patent Jurisdiction
United States Patent and Trademark Office
Patent Number
7620791
Patent Primary Examiner
Pierre-Michel Bataille
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