US Patent 7623381 Non-volatile memory device and method of erasing the same

A non-volatile memory device includes planes, a control logic circuit, a high voltage generator, and a X-decoder. The planes have a plurality of memory cell blocks, respectively. The control logic circuit outputs a row address, which allows a block address to select the same memory cell blocks from different planes at substantially the same time according to an external address signal including the block address and an erase mode bit signal, and an erase instruction signal. The high voltage generator generates erase voltages for an erase operation according to the erase instruction signal. The X-decoder applies the erase voltages to memory cell blocks selected by the row address.