An embodiment of a circuit switches between at least a first clock signal and a second clock signal in response to a corresponding switch command, and includes a selection module to select at a switch instant said second clock signal under the control of a signal selector. The circuit comprises a logic-based filter module located downstream of said selection module and configured to produce an outgoing clock signal filtered under the control of a filter signal and also includes a control module configured to receive said switch command and to send said select signal to said selection module delaying said switch instant by a first interval of time, said control module also being configured to send said active filter signal to said filter module in a second interval of time that comprises an edge of the first clock signal and an edge of the second clock signal.