Patent attributes
A data processing device with an efficient mechanism for controlling bus priority of multiple processors. The device has a data memory that is accessible to the processors via each processor's individual control bus and a common control bus. A bus selector is disposed between the individual control buses and the common control bus and controlled by a bus arbiter that resolves bus requests on the individual control buses from the processors attempting access to the data memory. The bus arbiter sends a selection command to the bus selector, thereby permitting a specified processor to reach the data memory. A bus monitor counts bus requests and conflicts between them, determines priority of each processor attempting access to the data memory according to the count results, and sends a wait command signal to low-priority processors so as to delay their access to the data memory.
