US Patent 7634695 Test apparatus and selection apparatus

There is provided a test apparatus for testing a memory under test that includes therein a plurality of blocks and one or more repairing columns. The test apparatus includes a testing section, a flag memory that stores thereon a flag indicating whether each column is defective, a counter memory that stores thereon the number of defective blocks in association with each column, a failure writing section that writes a flag indicating that a column is defective into the flag memory under a condition that one of the following conditions is satisfied: when a test result indicates that the column is defective; and when a flag stored on the flag memory in association with the column indicates that the column is defective, a counting section that increments the number of defective blocks stored on the counter memory in association with the column under a condition that the test result indicates that the column is defective and the flag indicating that the column is defective is not stored on the flag memory in association with the column, and a selecting section that selects columns to be replaced with the repairing columns based on the number of defective blocks stored in association with each column.