US Patent 7634749 Skew insensitive clocking method and apparatus
Patent 7634749 was granted and assigned to Cadence Design Systems on December, 2009 by the United States Patent and Trademark Office.
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Patent Inventor Names
Alex Kondratyev0
Jordi Cortadella0
Luciano Lavagno0
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Patent abstract
A method of designing a skew insensitive circuit is performed by designing a synchronous circuit including flip-flops and combinatorial logic and, for each flip-flop, inserting logic gates to receive a skewed clock signal and to locally derive non-overlapping clock phases from the skewed clock signal.
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US Patent 07634749 Skew insensitive clocking method and apparatus US Patent 7634749 Skew insensitive clocking method and apparatus
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Patent Number
076347490
Patent Number
76347490
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Is a
Current Assignee
Patent Jurisdiction
Patent Number
076347490
Date of Patent
December 15, 2009
0Patent Application Number
110975140
Date Filed
April 1, 2005
0Official Website
Patent Primary Examiner
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US Patent 07634749 Skew insensitive clocking method and apparatus
Infobox
Is a
Current assignee
Patent jurisdiction
Patent number
07634749
Date of patent
December 15, 2009
Patent application number
11097514
Date Filed
April 1, 2005
Patent primary examiner
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