US Patent 7639252 Unified tessellation circuit and method therefor

A hardware tessellation circuit serves as a unified hardware parametric coordinate generator for providing parametric coordinates for tessellation. The tessellation circuit includes control logic that receives tessellation instruction information, such as an instruction indicating which type of multiple tessellation operations to perform, on an incoming primitive wherein the different types of tessellation include discrete tessellation, continuous tessellation and adaptive tessellation. The tessellation circuit also includes shared tessellation logic that is controlled by the control logic, and includes a plurality of shared logic units, such as arithmetic logic units, that are controllable by the control logic based on the type of tessellation detected to be used for the incoming primitive. The shared tessellation logic is controlled to reuse at least some of the logic units for two different tessellation operations defined by the tessellation type information.