Is a
Patent attributes
Current Assignee
Patent Jurisdiction
Patent Number
Patent Inventor Names
Satoshi Masuda0
Masayasu Hojo0
Naofumi Kobayashi0
Ryuji Shimizu0
Haruhiko Abe0
Hideaki Konishi0
Date of Patent
December 29, 2009
0Patent Application Number
117177690
Date Filed
March 14, 2007
0Patent Primary Examiner
Patent abstract
In a delay failure test circuit, a delay failure test between two clock domains among a plurality of clock domains having different operation clock rates is performed. The delay failure test circuit inputs, to a first clock domain, a clock signal having only a launch edge for transferring data from the first clock domain to a second clock domain, and to input, to the second clock domain, a clock signal having only a capture edge for capturing the data.
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