Patent attributes
The present invention provides an integrated memory cell array comprising: a semiconductor substrate; a plurality of cell transistor devices including: a pillar formed in said semiconductor substrate; a gate trench surrounding said pillar; a first source/drain region formed in an upper region of said pillar; a gate dielectric formed on the bottom of said gate trench and surrounding a lower region of said pillar; a gate formed on said gate dielectric in said gate trench and surrounding a lower region of said pillar; and a second source/drain region formed in an upper region of said semiconductor substrate adjoining said gate trench; a plurality of bitlines being connected to respective first groups of first source/drain regions of said cell transistor devices; a plurality of wordlines connecting the respective gates of second groups said cell transistor devices; and a plurality of cell capacitor devices being connected to the second source/drain regions of said cell transistor devices.
