US Patent 7644263 Storage control system and boot control system

A PLD is interposed on the communication route between a microprocessor (hereinbelow called MP) and boot memories. The boot memories store MP start-up data needed to start up the MP and start-up protection code constituting protection code for the MP start-up data. The PLD reads the MP start-up data and the start-up protection code thereof from the boot memories, performs, in hardware fashion, a check of the validity of the MP start-up data using this start-up protection code and, if a negative check result is obtained, resets the MP and if a positive check result is obtained, inputs the start-up data that is thus read to the MP.