Patent attributes
A latch circuit (1) comprising a first input device (10a) in a first branch (4a) and a second input device (10b) in a second branch (4b). The latch circuit comprises a first estimator unit (40a) adapted to generate a first estimate of a current generated by the first input device (10a) and a second estimator unit (40b) adapted to generate a second estimate of a current generated by the second input device (10b). The latch circuit further comprises a control-voltage unit (50) operatively connected to the first and the second estimator unit (40a, 40b). The control-voltage unit is adapted to generate a control voltage based on a sum of the first estimate and the second estimate. Further, the latch circuit (1) comprises a first and a second voltage-controlled current unit (30a, 30b) adapted to generate currents at least based on the control voltage. The first voltage-controlled current unit (30a) is operatively connected to the first branch (4a). The second voltage-controlled current unit (30b) is operatively connected to the second branch (4b). A method for compensation for common-mode variations in the latch circuit (1) is also disclosed.
