US Patent 7650255 Automatic selective retest for multi-site testers

A method of multi-site testing a batch of semiconductor units using a multi-site automated tester (100). The tester (300) includes a handler (320) coupled to a contactor (330) including a first plurality of contact sites. The method includes the step of loading the first plurality of units into the first plurality of contact sites (201). The first plurality of units are simultaneously tested (202) using a test program to determine bin information for each of the first plurality of units, wherein the bin information defines each of the first plurality units as being a passed unit or a reject unit. The passed units are offloaded from respective contact sites of the first plurality of contact sites to create vacant contact sites (203), while keeping the reject unit(s) at respective contact sites of the first plurality of contact sites. Untested units from the batch are then loaded to fill the vacant contact sites (204). Simultaneously, the reject units retested and untested units are tested using the test program (205).