US Patent 7650581 Method for modeling and verifying timing exceptions

Patent 7650581 was granted and assigned to Atrenta on January, 2010 by the United States Patent and Trademark Office.

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Patent

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Current Assignee

Atrenta

Patent Jurisdiction

United States Patent and Trademark Office

Patent Number

76505810

Patent Inventor Names

Solaiman Rahim0

Mayank Jain0

Date of Patent

January 19, 2010

Patent Application Number

117490900

Date Filed

May 15, 2007

Patent Primary Examiner

‌

Thuan Do

Patent abstract

A method and system for timing exception verification in integrated circuit (IC) designs included verification of functional false paths as well as multi-cycle paths (MCPs). A false path or a MCP is modeled to a satisfiability formula and the formula is validated using a Boolean satisfiability solver. Time required for timing exception verification can be significantly reduced.

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