Patent attributes
A semiconductor device comprises multiple memory cell blocks including multiple memory cells for storing a predetermined amount of data. Each of the memory cell blocks having three or more inputs and three or more outputs includes two readout address decoders as to the memory cells internally, stores truth table data for outputting a desired logical value as to predetermined address input, and is configured so as to operate as a logic circuit. Also, the memory cells include two readout word lines corresponding to the two readout address decoders, and in the case of the voltage of both of the two readout word lines being applied, the data held at this time is read out from readout data lines. Further, between the memory cell blocks is connected such that the three or more outputs from one memory cell block are input to three or more other memory cell blocks.
