US Patent 7653523 Method for calculating high-resolution wafer parameter profiles
Patent 7653523 was granted and assigned to LSI Corporation on January, 2010 by the United States Patent and Trademark Office.
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Patent abstract
An embodiment of the present invention provides a method to utilize data from many different die sizes and products so that highly detailed wafer profiles can be generated that have an improved signal to noise ratio and spatial resolution. Instead of being limited to single die size like normal wafer maps, this method takes advantage of multiple die sizes and their variation in placement on the wafer to increase the information available about the wafer patterns.
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US Patent 07653523 Method for calculating high-resolution wafer parameter profiles US Patent 7653523 Method for calculating high-resolution wafer parameter profiles
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Patent Number
0765352300
Patent Number
765352300
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Infobox
Is a
Current Assignee
Patent Jurisdiction
Patent Number
076535230
Date of Patent
January 26, 2010
0Patent Application Number
107363860
Date Filed
December 15, 2003
0Official Website
Patent Primary Examiner
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Infobox
Is a
Current Assignee
Patent Jurisdiction
Patent Number
076535230
Date of Patent
January 26, 2010
0Patent Application Number
107363860
Date Filed
December 15, 2003
0Official Website
Patent Primary Examiner
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US Patent 07653523 Method for calculating high-resolution wafer parameter profiles
Infobox
Is a
Current assignee
Patent jurisdiction
Patent number
07653523
Date of patent
January 26, 2010
Patent application number
10736386
Date Filed
December 15, 2003
Patent primary examiner
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