US Patent 7653785 Reconfigurable cache controller utilizing multiple ASIC SRAMS

An application specific integrated circuit (ASIC) is configured to perform image processing tasks on a printer or other multi-function device. The ASIC includes a processor, a dedicated cache memory, a cache controller and additional Static Random Access Memory (SRAM) normally employed in image processing tasks. This additional SRAM may be dynamically allocated as a cache memory when not otherwise occupied.