Patent attributes
The through holes in an array manner in the signal layer within the chip-interposed region on a substrate of a BGA package comprise a ball pads array having a plurality of ball pads and a vias array. The vias array has a plurality of vias located interlaces with the ball pads array. The outermost portions of the chip-interposed region are designed in such a manner to have at least two rings of vias for signal transmission and power connection. The interval between every two adjacent vias in the ring is not less than twice of the distance of two ball pads. Upon such an arrangement, the BGA package can have a plurality of dissipation channels that can increase dissipation space, dissipate quickly the heat generated from the IC, and transmit well for signal and power.
