Patent attributes
A system may include a processor node, and may also include an input/output (I/O) node including a processor and an I/O device. The processor and I/O nodes may each include a respective cache memory configured to cache a system memory and a respective cache coherence controller. The system may further include interconnect through which the nodes may communicate. In response to detecting a request for the I/O device to perform a DMA write operation to a coherence unit of the I/O node's respective cache memory, and in response to determining that the coherence unit is not modified with respect to the system memory and no other cache memory within the system has read or write permission corresponding to a copy of the coherence unit, the I/O node's respective cache coherence controller may grant write permission but not read permission for the coherence unit to the I/O node's respective cache memory.
