US Patent 7664204 Adaptive timing using clock recovery

Circuits and methods are provided for adjusting a frequency of a local clock signal in approximating a frequency of a host clock signal. A phase locked loop generates a local clock signal having a first phase and a first frequency. An offset adjustment circuit receives timing information relating the local clock signal to an incoming data signal and calculates a phase offset and a frequency offset indicative of adjustments to be made to the local clock signal. A first phase interpolator generates a receive clock signal from the local clock signal, the receive clock signal having a second phase and a second frequency responsive to the phase and frequency offsets. A second phase interpolator generates a transmit clock signal from the local clock signal having a third frequency responsive to the frequency offset.