US Patent 7667307 Semiconductor device
Patent 7667307 was granted and assigned to Renesas Technology Corp on February, 2010 by the United States Patent and Trademark Office.
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To actualize a reduction in the on-resistance of a small surface mounted package having a power MOSFET sealed therein. A silicon chip is mounted on a die pad portion integrated with leads configuring a drain lead. The silicon chip has, on the main surface thereof, a source pad and a gate pad. The backside of the silicon chip configures a drain of a power MOSFET and bonded to the upper surface of a die pad portion via an Ag paste. A lead configuring a source lead is electrically coupled to the source pad via an Al ribbon, while a lead configuring a gate lead is electrically coupled to the gate pad via an Au wire.
US Patent 07667307 Semiconductor device US Patent 7667307 Semiconductor device
US Patent 07667307 Semiconductor device
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