US Patent 7670760 Treatment for reduction of line edge roughness
Patent 7670760 was granted and assigned to Freescale Semiconductor on March, 2010 by the United States Patent and Trademark Office.
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Patent abstract
A method for reducing line edge roughness (LER) in a layer of photoresist is provided. In accordance with the method, a layer of photoresist is applied to a substrate. The layer of photoresist is then patterned and annealed in an atmosphere comprising at least one gas selected from the group consisting of hydrogen, nitrogen and fluorine-containing materials. Preferably, the anneal is performed after patterning the photoresist, but either immediately after, or subsequent to, the trim.
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Patent Inventor Names
Brian J. Fisher0
James E. Vasek0
Jinmiao James Shen0
Jonathan L. Cobb0
Mark D. Hall0
Mehul D. Shroff0
Vikas R. Sheth0
William D. Darlington0
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US Patent 07670760 Treatment for reduction of line edge roughness US Patent 7670760 Treatment for reduction of line edge roughness
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Patent Number
07670760
Patent Number
7670760
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Official Website
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US Patent 07670760 Treatment for reduction of line edge roughness
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Is a
Current assignee
Patent jurisdiction
Patent number
07670760
Date of patent
March 2, 2010
Patent application number
11369513
Date Filed
March 6, 2006
Patent primary examiner
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