US Patent 7672694 Low power chip architecture

An architecture for selectively powering a receive module (108) is disclosed. The architecture comprises the receive module (108) which is functionally adapted, while power is applied to the receive module (108) by a power module (601), and after a power-up time interval has elapsed, to process a traffic packet. The architecture further comprises the power module (601) that is adapted to apply power to the receive module 108 dependent upon arrival of a wake-up packet.