Patent attributes
In a semiconductor device of the present invention, an N type epitaxial layer is divided into a plurality of element formation regions by an isolation region. In one of the element formation regions, an NPN transistor is formed. Around the NPN transistor, a protection element having a PN junction region is formed. The PN junction region has a junction breakdown voltage lower than that of a PN junction region of the NPN transistor. By use of this structure, when negative ESD surge is applied to a pad for a base electrode, the PN junction region of the protection element breaks down. Accordingly, the NPN transistor can be protected.