US Patent 7675787 Two-bits per cell not-and-gate (NAND) nitride trap memory

A non-volatile memory array includes a semiconductor substrate having a main surface, a first source/drain region and a second source/drain region. The second source/drain region is spaced apart from the first source/drain region. A well region is disposed in a portion of the semiconductor substrate between the first source/drain region and the second source/drain region. A plurality of memory cells are disposed on the main surface above the well region. Each memory cell includes a first oxide layer formed on the main surface of the substrate, a charge storage layer disposed above the first oxide layer relative to the main surface of the semiconductor substrate and a second oxide layer disposed above the charge storage layer relative to the main surface of the semiconductor substrate. A plurality of wordlines are disposed above the second oxide layer relative to the main surface of the semiconductor substrate.