Patent attributes
A method in an integrated circuit for generating an address value having a contiguous address range from a first selection result and a second selection result each being an one-of-k selection result includes selecting multiple multiplication factors being power-of-two multiplication factors and the sum of the multiplication factors being equal to k; shifting the first selection result towards the most significant bit by each of the multiplication factors to generate multiple shifted input values where each shifted input value is shifted towards the most significant bit by one of the multiplication factors; adding the shifted input values and the second selection result; and generating the address value having a contiguous address range. The method can be extended to combine more than two selection results by applying the shifting and addition steps in a hierarchical manner.
