US Patent 7681067 Bus system

It is so arranged that an appropriate deadline is assured with little consumption of power. A register (24) for remaining transfer time senses time that remains up to a limit by which data is to be transferred. A register (25) for remaining amount of data transfer senses the remaining amount of data that is to be transferred. The clock of the processing module is changed over dynamically based upon the remaining time sensed by the remaining transfer time register (24) and the remaining amount of transfer data sensed by the remaining transfer amount register (25).