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US Patent 7683659 Integrated circuits with jitter-reducing balancing logic

Patent 7683659 was granted and assigned to Altera on March, 2010 by the United States Patent and Trademark Office.

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Patent
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Patent attributes

Current Assignee
Altera
Altera
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
76836590
Patent Inventor Names
Peter Boyle0
Eugene V. Gomez0
Iliya G. Zamek0
Nafira Daud0
Date of Patent
March 23, 2010
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Patent Application Number
120607910
Date Filed
April 1, 2008
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Patent Primary Examiner
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Daniel D Chang
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Patent abstract

Integrated circuits contain core logic that is powered using a power supply signal. The core logic contains simultaneously switching circuitry. The simultaneously switching circuitry contributes to noise on the power supply signal. Balancing circuitry may be provided on the integrated circuit to compensate for the simultaneously switching circuitry in the core logic. The balancing circuitry may receive an input signal that is out of phase with respect to the input to the core logic. As the balancing circuitry switches out of phase with the simultaneously switching circuitry of the core logic, the noise contribution from the core logic is compensated and power supply noise on the power supply signal is minimized.

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