US Patent 7685489 Semiconductor integrated circuit and testing method

A semiconductor integrated circuit includes: an input/output cell that is included in a path captured during propagation delay testing and that has an output-stage buffer on an output bus; and a terminal connected to the output bus and an input bus of the input/output cell. An external load or a testing device is connectable to the terminal. The input/output cell has a switching part that is capable of switching between a first path that loops back at an output side of the output-stage buffer and a second path that loops back at an input side of the output-stage buffer. The first path is selected during normal operation and the second path is selected during the propagation delay testing.