Patent attributes
Circuitry and methods are disclosed for capturing data from a double-data rate signal received from a source circuit, converting the double-data rate signal to single and/or half rate data signals, and re-synchronizing the data to the destination circuit's clock signal. In one embodiment, a first set of registers converts a double-data rate signal synchronized to a full-rate clock signal to two single-data rate signals. A second set of registers converts the single-data rate signals to four half-data rate signals. A third set of registers synchronizes the half-rate data signals to a half-rate clock signal. In another embodiment, methods and circuitry are provided for determining the position of a data valid window of the half-data rate intermediate signals relative to the rising and falling edges of the half-rate clock signal and using that determination to select half-data rate intermediate signals captured on either a rising or falling edge of the half-rate clock signal, depending on which will provide greater accuracy.
