Patent attributes
A pipeline processing system capable of high speed operation and capable of realizing a reduction of power consumption and an information processing apparatus to which this is applied, wherein a decoder/encoder circuit accesses a first memory and a second memory in parallel in accordance with status information at decoding processing to perform decoding processing, stores the data after processing in a tracking memory, then transfers the data stored in the tracking memory to a host apparatus according to a request from the host apparatus, while writes the user data transferred in unit of blocks from the host apparatus in a third memory serving as a tracking buffer to start the encoder processing in the case of the encoding processing, accesses a plurality of memories in parallel in accordance with the status information to perform the encoding processing, and outputs the same to a clock generation circuit.
